Vhdl Program For 8 Bit Up Down Counter

I am having some trouble debugging this program. I was given an assignment to read test vectors from a text file to test a program. The program and test bench code is written below. I cannot figure out why my simulation is coming up blank.

May 29, 2017. This page of VHDL source code covers 4 bit up down counter vhdl code. VHDL Up/Down Counter. Created on: 1. Designing BCD UP/DOWN Counters. Designing a VHDL model for the MC14510B and a Cascaded 8-bit. Implement a Presettable Cascaded 8-bit BCD Up/Down. This page contains VHDL tutorial, VHDL Syntax, VHDL Quick Reference, modelling memory and FSM, Writing Testbenches in VHDL, Lot of VHDL Examples and VHDL in One Day Tutorial.

No errors, the simulation window comes up, but it is blank. Cvija I Rada Manojlovic Nema Te Download Mp3. Any idea what the problem may be? Module: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity PAR is Port ( data: in STD_LOGIC_VECTOR (3 downto 0); parity: out STD_LOGIC); end PAR; architecture Behavioral of PAR is begin proc: process variable count: bit; begin for i in data'range loop if data(i)='1' then count:=not count; end if; end loop; if count='0' then parity '0'); --Outputs signal parity: std_logic; -- No clocks detected in port list. Replace below with -- appropriate port name BEGIN -- Instantiate the Unit Under Test (UUT) uut: PAR PORT MAP ( data =>data, parity =>parity ); TB: process file vec_file: text; variable buf_in: line; variable testv: std_logic_vector(0 to 4); begin file_open(vec_file,'PAR_file.txt,', read_mode); while not endfile (vec_file) loop readline (vec_file, buf_in); read(buf_in,testv); data(3).